Method of detecting phase difference, phase detector for performing the same and clock-and-data recovering device including the phase detector

Abstract

First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45° may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.