The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

Nov. 25, 2003
Applicants:

Hiromichi Watanabe, Kobe, JP;

Yoshifumi Fukatsu, Kobe, JP;

Hideaki Kaino, Kobe, JP;

Inventors:

Hiromichi Watanabe, Kobe, JP;

Yoshifumi Fukatsu, Kobe, JP;

Hideaki Kaino, Kobe, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention concerns a substrate for circuit wiring in which an electronic component is mounted, by soldering, to a wiring pattern formed on an insulated layer deposited over a metallic substrate. A silica-based filler and a rubber-based filler are added in the insulated layer to reduce the linear thermal expansion of the layer and increase its elastic modulus. The mounting portion of an electronic component is molded with a resin material to which a silica-based filler has been added, and which thus has a coefficient of linear thermal expansion smaller than the coefficient of linear thermal expansion of the insulated layer. This serves to alleviate the stress caused by the linear thermal expansion of the metallic substrate, and thereby to prevent separation from occurring between the insulated layer and the metallic substrate, as well as between the insulated layer and the wiring pattern, when subjected to a high-temperature environment.


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