The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2006

Filed:

Nov. 21, 2001
Applicants:

Kotaro Fujiwara, Tokyo, JP;

Yuuichi Tachi, Tokyo, JP;

Kazuaki Miyabe, Tokyo, JP;

Tamiki Kobayashi, Tokyo, JP;

Inventors:

Kotaro Fujiwara, Tokyo, JP;

Yuuichi Tachi, Tokyo, JP;

Kazuaki Miyabe, Tokyo, JP;

Tamiki Kobayashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

When a decoding circuit () decodes an instruction code stored in a pipeline register (), the decoding circuit () decodes the device address. Based on this, it is decided which one of the device information of a RAM () and a RAM () is to be used. When the area of the RAM () has been assigned, the decoding circuit () outputs a signal showing that the number of stop of pipeline processing is 0, unlike the assignment of the RAM (). Therefore, a pipeline register section () does not set the pipeline stop signal to 1. Consequently, the reading of the instruction code from the RAM () and the pipeline processing are not interrupted. As a result, it is possible to realize a structure in which execution of a high-speed processing is possible and a compact/low-cost structure in the same hardware.


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