The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
May. 09, 2003
Michael W. Deur, Leander, TX (US);
David Hayner, Austin, TX (US);
Donald Louis Tietjen, Austin, TX (US);
Michael W. Deur, Leander, TX (US);
David Hayner, Austin, TX (US);
Donald Louis Tietjen, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method and apparatus for interconnecting circuit portions () within a data processing system () using a master/slave interfaces () which may be configured by way of configuration registers (). External address generation circuitry () and internal address generation circuitry () may be used to generate externally used addresses and internally used addresses, respectively. A circuit portion (e.g.) may have a plurality of interfaces () which may operate as a slave interface (e.g.) or as a master interface (e.g.). A same master/slave interface structure and protocol (e.g.) may be duplicated and individually configured to be used to communicate among all of the circuit portions () within a data processing system ().