The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Mar. 25, 2002
Applicants:
Liang T. Chen, Saratoga, CA (US);
William Kwei-cheung Lam, Newark, CA (US);
Thomas M. Mcwilliams, Menlo Park, CA (US);
Inventors:
Liang T. Chen, Saratoga, CA (US);
William kwei-cheung Lam, Newark, CA (US);
Thomas M. McWilliams, Menlo Park, CA (US);
Assignee:
Sun Microsystems, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.