The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2006

Filed:

Mar. 02, 2005
Applicants:

John S. Austin, Winooski, VT (US);

Ram Kelkar, South Burlington, VT (US);

Pradeep Thiagarajan, South Burlington, VT (US);

Inventors:

John S. Austin, Winooski, VT (US);

Ram Kelkar, South Burlington, VT (US);

Pradeep Thiagarajan, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.


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