Method for distributing clock signals to flip-flop circuits

Abstract

A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.