The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Jun. 30, 2005
Katsuhiko Manabe, Hyogo-ken, JP;
Tomonari Katoh, Osaku-fu, JP;
Minoru Sugiyama, Hyogo-ken, JP;
Makoto Matsushima, Hyogo-ken, JP;
Tadayoshi Ueda, Hyogo-ken, JP;
Katsuhiko Manabe, Hyogo-ken, JP;
Tomonari Katoh, Osaku-fu, JP;
Minoru Sugiyama, Hyogo-ken, JP;
Makoto Matsushima, Hyogo-ken, JP;
Tadayoshi Ueda, Hyogo-ken, JP;
Ricoh Company, Ltd., Tokyo, JP;
Abstract
A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.