The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Sep. 14, 2004
Jerimy Nelson, Fort Collins, CO (US);
Mark D. Frank, Longmont, CO (US);
Peter Shaw Moldauer, Wellington, CO (US);
Gary Taylor, Windsor, CO (US);
David Quint, Fort Collins, CO (US);
Jerimy Nelson, Fort Collins, CO (US);
Mark D. Frank, Longmont, CO (US);
Peter Shaw Moldauer, Wellington, CO (US);
Gary Taylor, Windsor, CO (US);
David Quint, Fort Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.