The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Aug. 05, 2004
Shinichiro Suga, Kasugai, JP;
Takumi Kawai, Kasugai, JP;
Shinichiro Suga, Kasugai, JP;
Takumi Kawai, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction at a pitch Yin the Y direction and second gate wiringsare disposed in the Y direction with two pieces as a pair such that they meander at a pitch Xin the X direction. The meandering of the second gate wiringis formed so as to sandwich the bent portionssubstantially in the center of the pitch Y. A bottle-like shape diffusion layer region in which the wide-width region and narrow-width region are combined is sectioned by adjacent first and second wirings. A contactfor connecting the diffusion layer region to the wiring layeris disposed in the wide-width region and wiring layersare disposed such that two rows run in parallel in the X direction. A diffusion layer region is a different electrode region from diffusion layer regions adjacent on four sides thereby forming a MOS transistor. Consequently, a horizontal MOS transistor excellent in current drivability for each unit region and having a slight ON resistance is constructed.