The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Sep. 17, 2004
Cheng-chih Huang, Taipei, TW;
Sheng-wei Yang, Taipei, TW;
Chen-chou Huang, Taipei, TW;
Sheng-tsung Chen, Tainan, TW;
Cheng-Chih Huang, Taipei, TW;
Sheng-Wei Yang, Taipei, TW;
Chen-Chou Huang, Taipei, TW;
Sheng-Tsung Chen, Tainan, TW;
Nanya Technology Corporation, Taoyuan, TW;
Abstract
A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.