The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2006

Filed:

Jul. 16, 2002
Applicants:

Richard F. Roth, Brookline, NH (US);

Sepehr Kiani, Watertown, MA (US);

Inventors:

Richard F. Roth, Brookline, NH (US);

Sepehr Kiani, Watertown, MA (US);

Assignee:

Amphenol Corporation, Wallingford, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/36 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of a fiber optic connection system of the present invention, there is provided a first fiber optic connector attachable to a first printed circuit board and a second fiber optic connector attachable to a second printed circuit board and mateable to the first fiber optic connector. The first fiber optic connector has separable first wafer modules, each of which hold at least one optical fiber, and separable first latching modules removably attached to the separable first wafer modules. The second fiber optic connector includes separable second wafer modules, each of which hold at least one optical fiber, and separable second latching modules removably attached to the separable second wafer modules. The separable second latching modules are engageable to the separable first latching modules to mate the first and second fiber optic connectors. Although not required, the fiber optic connection system can also include a first module carrier, to which is attachable the separable first wafer modules and the separable first latching modules, and a second module carrier, to which is attachable the separable second wafer modules and the separable second latching modules.


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