The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Jan. 08, 2004
Chikaaki Kodama, Kasukabe, JP;
Akihiro Yoshitake, Kawasaki, JP;
Chikaaki Kodama, Kasukabe, JP;
Akihiro Yoshitake, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A layer defining unit defines different layer numbers to oblique wiring diagrams and via cell diagrams which are included in layout data of a semiconductor integrated circuit design. A first diagram blending unit fetches diagram data including the oblique wiring diagrams and the via cell diagrams from the layout data, synthesizes the diagrams every same layer number, and blends them in overlapped portions. An oblique wiring verifying unit verifies an interval between the oblique wiring diagrams blended by the first diagram blending unit by an allowable minimum interval value S. A second diagram blending unit synthesizes the verified oblique wiring diagram and the via mat diagram of the via cell, thereby forming an oblique wiring mask diagram blended in an overlapped portion. A blended diagram verifying unit verifies an interval between the oblique wirings having projecting portions by the via cells of the oblique wiring mask diagram blended by the second diagram blending unit by an allowable minimum interval value T (where, T<S).