The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Feb. 14, 2003
Applicant:
Minoru Kozaki, Suwa, JP;
Inventor:
Minoru Kozaki, Suwa, JP;
Assignee:
Seiko Epson Corporation, , JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 5/04 (2006.01);
U.S. Cl.
CPC ...
Abstract
A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck–Cka delay time detection signal DTcorresponding to a delay time 5τ from the multi-phase clock Ckto the multi-phase clock Ckis generated. An Upsignal is forcibly output to a charge pump circuit CPbased on this delay time detection signal DTand the output of a Down1 signal is suppressed.