The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Dec. 18, 2003
Christopher S. Maclellan, Walpole, MA (US);
Avinash Kallat, Marlborough, MA (US);
Almir Davis, Quincy, MA (US);
Stephen L. Scaringella, Holliston, MA (US);
Christopher S. MacLellan, Walpole, MA (US);
Avinash Kallat, Marlborough, MA (US);
Almir Davis, Quincy, MA (US);
Stephen L. Scaringella, Holliston, MA (US);
EMC Corporation, Hopkinton, MA (US);
Abstract
A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.