Interrupt-based phase-locked frequency multiplier

Abstract

A method and system utilize a processor's digital timer and two interrupts to form a frequency multiplier. The first interrupt's processing time window is definable by a first number of counts Cof the digital timer while the second interrupt's processing time window is definable by a second number of counts Cof the digital timer. A count value CV utilized by the system/method is based on a desired frequency multiplier N, the timer clock rate, and the time required for one cycle of an input signal. The first interrupt is triggered upon completion of one cycle of the input signal at which point the processing time window associated therewith begins. The second interrupt is triggered each time the timer's overflow signal is generated at which point the processing time window associated with the second interrupt begins. During the occurrence of the second interrupt's processing, the count value CV is modified to maintain the first interrupt's processing time window approximately centered between two of the second interrupt's processing time windows.