The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Dec. 20, 2004
Ross E. Teggatz, McKinney, TX (US);
Sanmukh M. Patel, Richardson, TX (US);
Rex M. Teggatz, Sachse, TX (US);
Suribhotla V. Rajasekhar, Plano, TX (US);
Valerian Mayega, Irving, TX (US);
Ross E. Teggatz, McKinney, TX (US);
Sanmukh M. Patel, Richardson, TX (US);
Rex M. Teggatz, Sachse, TX (US);
Suribhotla V. Rajasekhar, Plano, TX (US);
Valerian Mayega, Irving, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.