The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2006

Filed:

Aug. 27, 2004
Applicants:

Yido Koo, Seoul, KR;

Hyungki Huh, Seoul, KR;

Kang Yoon Lee, Seoul, KR;

Jeong-woo Lee, Seoul, KR;

Joonban Park, Seoul, KR;

Kyeongho Lee, Seoul, KR;

Inventors:

Yido Koo, Seoul, KR;

Hyungki Huh, Seoul, KR;

Kang Yoon Lee, Seoul, KR;

Jeong-Woo Lee, Seoul, KR;

Joonban Park, Seoul, KR;

Kyeongho Lee, Seoul, KR;

Assignee:

GCT Semiconductor, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H03B 7/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.


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