The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Apr. 29, 2005
Toshihiro Morisawa, Yokohama, JP;
Hisahiko Abe, Tokyo, JP;
Kosaku Tachikawa, Hitachinaka, JP;
Toshihiro Nakajima, Hitachinaka, JP;
Toshihiro Morisawa, Yokohama, JP;
Hisahiko Abe, Tokyo, JP;
Kosaku Tachikawa, Hitachinaka, JP;
Toshihiro Nakajima, Hitachinaka, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
In a wafer polishing method, a within-wafer distribution model of a removal rate and a within-wafer distribution model of a polishing process are selected, and a within-wafer distribution of a removal rate is obtained by determining parameters of a within-wafer distribution model of a removal rate based on the within-wafer distribution of the film thickness before/after CMP, polishing condition data, and the selected within-wafer distribution model of the polishing process of the polished wafer. Then, a film thickness in the polishing process is estimated from passage of time based on the obtained within-wafer distribution of the removal rate, the selected within-wafer distribution model of the polishing process, and the film thickness before CMP of the wafer to be processed, thereby determining the polishing conditions with a restriction that the film thickness at each position in the within-wafer distribution of the film thickness after CMP satisfies the control limit.