The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2006
Filed:
Jul. 20, 2001
Rainer Topp, Reutlingen, DE;
Dirk Balszunat, Tuebingen, DE;
Stephan Ernst, Ostfildern, DE;
Achim Henkel, Reutlingen, DE;
Doerte Eimers-klose, Reutlingen, DE;
Reinhard Milich, Reutlingen, DE;
Rainer Topp, Reutlingen, DE;
Dirk Balszunat, Tuebingen, DE;
Stephan Ernst, Ostfildern, DE;
Achim Henkel, Reutlingen, DE;
Doerte Eimers-Klose, Reutlingen, DE;
Reinhard Milich, Reutlingen, DE;
Robert Bosch GmbH, Stuttgart, DE;
Abstract
A method of establishing an electric connection between electric terminals of a semiconductor component as part of an electric module and additional parts of the electric module by using a punched grid having internal terminal ends and external terminal ends that are electrically connected to the internal terminal ends by metal strip conductors, the semiconductor component and the punched grid are joined so that at least two electric terminals of the semiconductor component are positioned on corresponding internal terminal ends so that a slip-proof mounting of the semiconductor component on the two internal terminal ends is then possible, this mechanical mounting at the same time establishing an electric connection between the electric terminals of the semiconductor component and the internal terminal ends, whereby a metal strip grid, e.g., a punched grid, which, even before being joined to the semiconductor component, has already been embedded on at least one side in at least one partial area in a material that is not electrically conductive, is used as the metal strip grid. This procedure is used for bond-free contacting of semiconductor components for high-power applications in which a power loss of more than 1 Watt may occur.