The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2006

Filed:

Sep. 29, 2004
Applicants:

Qian Cui, San Jose, CA (US);

Sandeep Bhutani, Milpitas, CA (US);

Inventors:

Qian Cui, San Jose, CA (US);

Sandeep Bhutani, Milpitas, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.


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