Layout structure of bit line sense amplifier of semiconductor memory device

Abstract

A layout structure of a bit line sense amplifier is provided. According to an embodiment of the present invention, the layout structure of the bit line amplifier of a semiconductor memory device includes memory blocks structured by a plurality of cells, bit line pairs connected to the cells and a plurality of bit line sense amplifier blocks for sensing data of the cells, wherein each of the bit line sense amplifier blocks comprises: PMOS sense amplifier structured by first and second PMOS transistors; NMOS sense amplifier structured by first and second NMOS transistors; an IO line pair structured by an IO line and an IO bar line, which are placed between the PMOS sense amplifier and the NMOS sense amplifier; and a first IO switch and a second IO switch, which are connected to one of the bit line pair and the IO line pair, wherein a gate region of the first PMOS transistor, a gate region of the first NMOS transistor and the first IO switch are respectively arranged at a gate region of the second PMOS transistor, a gate region of the second NMOS transistor and the second IO switch in one direction only at predetermined spaces ΔP, ΔN and ΔI.