The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2006
Filed:
Jan. 17, 2003
Applicant:
Lester S. Sanders, Albuquerque, NM (US);
Inventor:
Lester S. Sanders, Albuquerque, NM (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output terminal, and a configuration terminal. The flip-flop is coupled to the clock gate. The flip-flop is configurable to trigger on at least one of a rising edge and a falling edge of a clock signal. The clock gate controllably gates the clock signal coupled to the clock terminal.