The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2006

Filed:

Jun. 30, 2004
Applicants:

Dipankar Bhattacharya, Macungie, PA (US);

Makeshwar Kothandaraman, Whitehall, PA (US);

John C. Kriz, Palmerton, PA (US);

Antonio M. Marques, Summit, NJ (US);

Bernard L. Morris, Emmaus, PA (US);

Inventors:

Dipankar Bhattacharya, Macungie, PA (US);

Makeshwar Kothandaraman, Whitehall, PA (US);

John C. Kriz, Palmerton, PA (US);

Antonio M. Marques, Summit, NJ (US);

Bernard L. Morris, Emmaus, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.


Find Patent Forward Citations

Loading…