The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2006
Filed:
Jan. 31, 2005
Shahram Mostafazadeh, San Jose, CA (US);
Shahram Mostafazadeh, San Jose, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A variety of techniques and structures are described that integrate an insulated pedestal into the back surface of integrated circuit dice. The die has an insulated integral pedestal formed therein that acts as a spacer. The pedestal has a footprint that is smaller than the total footprint of the die so that a portion of the active region of the die overhangs the pedestal. The geometry of the pedestal may be widely varied and in some embodiments, multiple pedestals may be provided on the stacked die. In another aspect, the pedestals are formed at the wafer level such that the pedestals are defined in the back surface of the wafer. Often, the thickness of the pedestals will be thicker than the portions of the wafer outside the pedestal areas. The described dice are particularly well suited for use in stacked die packages.