The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2006
Filed:
Feb. 13, 2004
Jayakannan Jayapalan, San Jose, CA (US);
Liping LI, Campbell, CA (US);
Yow-juang Liu, San Jose, CA (US);
Jayakannan Jayapalan, San Jose, CA (US);
Liping Li, Campbell, CA (US);
Yow-Juang Liu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
The present invention includes a method and apparatus for measuring a parasitic inductance associated with a portion of an integrated circuit fabricated on a semiconductor substrate. A test chip for measuring the parasitic inductance is fabricated together with the integrated circuit on the semiconductor substrate. The test chip includes an LC oscillator circuit having at least one substructure that resembles the portion of the integrated circuit and at least one varactor having a capacitance adjustable by a control voltage. When the LC oscillator circuit is connected to the control voltage source and the control voltage is at a certain level, an oscillation is generated in the LC oscillator and the frequency of oscillation can be used to determine the parasitic inductance associated with the portion of the integrated circuit.