The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2006

Filed:

Aug. 06, 2003
Applicants:

Timothy Thurgate, Sunnyvale, CA (US);

Nga-ching Wong, San Jose, CA (US);

Inventors:

Timothy Thurgate, Sunnyvale, CA (US);

Nga-Ching Wong, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate; forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter-doping implant region is substantially on the drain side and wherein the counter-doping reduces the net channel impurity concentration on the drain side.


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Thurgate, Timothy. (2006). Structure and method to reduce drain induced barrier lowering (U.S. Patent No. 7067381). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7067381

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