The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2006
Filed:
Nov. 15, 2004
Omar Zia, Austin, TX (US);
Nigel G. Cave, Austin, TX (US);
Lawrence Cary Gunn, Iii, Encinitas, CA (US);
Omar Zia, Austin, TX (US);
Nigel G. Cave, Austin, TX (US);
Lawrence Cary Gunn, III, Encinitas, CA (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.