The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Apr. 25, 2001
Mar Hershenson, Los Altos, CA (US);
Arash Hassibi, Mountain View, CA (US);
Andre Hentz, Mountain View, CA (US);
Stephen Boyd, Stanford, CA (US);
Mar Hershenson, Los Altos, CA (US);
Arash Hassibi, Mountain View, CA (US);
Andre Hentz, Mountain View, CA (US);
Stephen Boyd, Stanford, CA (US);
Barcelona Design, Inc., Mountain View, CA (US);
Abstract
A method is described for optimal simultaneous design and floorplanning of integrated circuits. The method is based on formulating the problem as a geometric program, which then can be solved numerically with great efficiency. Prior work discloses the design of many different analog circuit cells such as operational amplifiers, spiral inductors, and LC oscillators which can be cast as geometric programs. The present disclosure adds to this layout floorplanning constraints in posynomial form that can be mixed with design constraints for different analog circuits. This allows the simultaneous design and floorplanning of numerous analog circuits using geometric programming. Thus, the design and floorplanning can be performed optimally in a single step.