The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Dec. 05, 2001
David O. Sluiter, Superior, CO (US);
Robert W. Moss, Longmont, CO (US);
Mark J. Kwong, Santa Clara, CA (US);
Peter Korger, Frederick, CO (US);
Christopher M. Giles, Lafayette, CO (US);
David O. Sluiter, Superior, CO (US);
Robert W. Moss, Longmont, CO (US);
Mark J. Kwong, Santa Clara, CA (US);
Peter Korger, Frederick, CO (US);
Christopher M. Giles, Lafayette, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.