Precision jitter-free frequency synthesis

Abstract

An electronic system () includes a phase-locked loop () and a frequency synthesis circuit (), for generating a jitter-free output clock (CLKCLK) at a desired frequency. The phase-locked loop () includes a voltage-controlled oscillator () that produces a number (N) of equally spaced clock phases at a frequency (f) that depends also upon a programmable feedback frequency divider () and a prescale divider (). The frequency synthesis circuit () generates the output clock (CLKCLK) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (), either itself or from a look-up table (), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error. The frequency of the output clock (CLKCLK) can be generated in a jitter-free manner, since only integer values are used in the frequency synthesis circuit (), at relatively low frequency error.