The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Mar. 24, 2004
Applicants:
Enver Krvavac, Lake Zurich, IL (US);
James E. Mitzlaff, Arlington Heights, IL (US);
Mark I. Van Horn, Arlington, TX (US);
Inventors:
Enver Krvavac, Lake Zurich, IL (US);
James E. Mitzlaff, Arlington Heights, IL (US);
Mark I. Van Horn, Arlington, TX (US);
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/14 (2006.01);
U.S. Cl.
CPC ...
Abstract
Apparatus and methods are described for biasing amplifiers with multiple outputs. A semiconductor die may include a reference Field Effect Transistor (FET) integrated on the semiconductor die and coupled to an amplifier integrated on the semiconductor die. A voltage offset circuit may also be integrated on the semiconductor die for determining the voltage needed to operate the amplifier.