The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Dec. 30, 2003
Andrew Crosland, Aylesbury, GB;
Roger May, Bicester, GB;
Stephane Caneau, London, GB;
Andrew Draper, Chesham, GB;
Edward Flaherty, Kingston Bagpuize, GB;
Andrew Crosland, Aylesbury, GB;
Roger May, Bicester, GB;
Stephane Caneau, London, GB;
Andrew Draper, Chesham, GB;
Edward Flaherty, Kingston Bagpuize, GB;
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.