Architecture and fabrication method of a vertical memory cell

Abstract

A vertical memory cell comprises a storage capacitor, the inner electrode of which is formed in a deep trench, and a vertical selector transistor. The selection transistor has an upper source/drain region and a lower source/drain region, which has emerged by outdiffusion of a dopant from the inner electrode. A gate electrode, which in each case controls a current flow between two assigned source/drain regions, is formed, in segments, as a segment of an addressing line arranged row-wise in active trenches. The provision of an auxiliary structure in the active trenches enables the addressing lines to be vertically positioned in the active trenches independently of a depth of the active trenches. Leakage currents which occur in overlap regions of the addressing lines with the inner electrode or the lower source/drain region are reduced.