The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7063751 B1

Date of Patent:

Jun. 20, 2006

Filed:

Apr. 26, 2002

Semiconductor substrate formed by epitaxially filling a trench in a semiconductor substrate with a semiconductor material after smoothing the surface and rounding the corners

Applicants:

Yasushi Urakami, Tokai, JP;

Shoichi Yamauchi, Obu, JP;

Hitoshi Yamaguchi, Obu, JP;

Nobuhiro Tsuji, Okazaki, JP;

Inventors:

Yasushi Urakami, Tokai, JP;

Shoichi Yamauchi, Obu, JP;

Hitoshi Yamaguchi, Obu, JP;

Nobuhiro Tsuji, Okazaki, JP;

Assignee:

Denso Corporation, Kariya, JP;

Attorney:

Posz Law Group, PLC

Primary Examiner:

Erik Kielin

Int. Cl.

CPC ...

H01L 29/12 (2006.01); H01L 29/30 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 29/04 (2006.01);

U.S. Cl.

CPC ...

Abstract

A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

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Urakami, Yasushi. (2006). Semiconductor substrate formed by epitaxially filling a trench in a semiconductor substrate with a semiconductor material after smoothing the surface and rounding the corners (U.S. Patent No. 7063751). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7063751

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