The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Dec. 30, 2002
David C. Bisbee, Princeton, MA (US);
Scot C. Tata, Blackstone, MA (US);
Erik C. Nelson, Upton, MA (US);
Thomas Delucia, Milford, MA (US);
Thomas E. Linnell, Northboro, MA (US);
William R. Tuccio, Sutton, MA (US);
Edward J. Claprood, Southboro, MA (US);
Enrico Difabio, Cranston, RI (US);
Brian Gallagher, Southboro, MA (US);
Lawrence G. Pignolet, Mapleville, RI (US);
David C. Bisbee, Princeton, MA (US);
Scot C. Tata, Blackstone, MA (US);
Erik C. Nelson, Upton, MA (US);
Thomas Delucia, Milford, MA (US);
Thomas E. Linnell, Northboro, MA (US);
William R. Tuccio, Sutton, MA (US);
Edward J. Claprood, Southboro, MA (US);
Enrico DiFabio, Cranston, RI (US);
Brian Gallagher, Southboro, MA (US);
Lawrence G. Pignolet, Mapleville, RI (US);
EMC Corporation, Hopkinton, MA (US);
Abstract
A data storage interface for coupling data between processors and a bank of disk. The interface includes a plurality of first directors coupled to the processors and a plurality of second directors coupled to the bank of disk drives. A cache memory is coupled between the plurality of first directors and the plurality of second directors. The interface includes a pair of independent power busses. At least one of the first or second directors is coupled to the pair of independent power busses. One portion of the disk drives in the bank is connected to only a first one of the pair of power buses and a different portion of the disk drives is connected to only the other one of the pair of power buses. A power circuit includes a pair of input terminals, each one being electrically connected to a corresponding one of the pair of independent power busses. The circuit includes an output terminal. A pair of switching transistor sections is provided. The transistor switching sections is serially connected between a corresponding one of the pair of input terminals and the output terminal. A logic network is provided for operating the switching sections to prevent current passing into one of the pair of input terminals from one of the power busses from passing into the other one of the power buses. The logic section operates the switching sections to prevent current from one of the pair of power buses to the one of the input terminals connected thereto from exceeding a predetermined value, and operates the switching sections to prevent a difference between a voltage at one of the input terminals and a voltage at the other one of the input terminals from exceeding a predetermined value.