The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7061118 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 13, 2006

Filed:

May. 03, 2004
Applicant:

Kazuhiro Masuda, Fujimi-machi, JP;

Inventor:

Kazuhiro Masuda, Fujimi-machi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device having a connection terminal and a substrate on which a circuit section and an electrode are stacked in this order, the circuit section having a multilayer interconnect structure, the electrode being conductively connected to the circuit section, and the connection terminal penetrating the substrate and being conductively connected to the electrode. Part of the connection terminal is formed simultaneously with an interconnect in an interconnect layer of the circuit section.


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Masuda, Kazuhiro. (2006). Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument (U.S. Patent No. 7061118). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7061118

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