The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Mar. 02, 2004
Yusuke Kawaguchi, Miura-gun, JP;
Norio Yasuhara, Kawasaki, JP;
Syotaro Ono, Yokohama, JP;
Shinichi Hodama, Yokohama, JP;
Akio Nakagawa, Fujisawa, JP;
Yusuke Kawaguchi, Miura-gun, JP;
Norio Yasuhara, Kawasaki, JP;
Syotaro Ono, Yokohama, JP;
Shinichi Hodama, Yokohama, JP;
Akio Nakagawa, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile