The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2006

Filed:

May. 10, 2005
Applicants:

Won-ju Cho, Daejeon, KR;

Chang-geun Ahn, Daejeon, KR;

Ki-ju Im, Daejeon, KR;

Jong-heon Yang, Daejeon, KR;

In-bok Baek, Daejeon, KR;

Seong-jae Lee, Daejeon, KR;

Inventors:

Won-ju Cho, Daejeon, KR;

Chang-geun Ahn, Daejeon, KR;

Ki-ju Im, Daejeon, KR;

Jong-heon Yang, Daejeon, KR;

In-bok Baek, Daejeon, KR;

Seong-jae Lee, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.


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