The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Sep. 30, 2003
Amit Singh, San Jose, CA (US);
Kamal Chaudhary, San Jose, CA (US);
Amit Singh, San Jose, CA (US);
Kamal Chaudhary, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method () of placing a circuit design can include the steps of identifying topological levels of a circuit design representation () and determining an arrival time for each input signal to a look up table within a circuit design representation (). The propagation delay associated with each pin of the look up table can be identified () such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (). The method can continue processing each look up table of an identified topological level () as well as each topological level of the circuit design representation ().