The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2006

Filed:

Dec. 26, 2001
Applicants:

Weiying Ding, Cupertino, CA (US);

Brad Vest, San Jose, CA (US);

Inventors:

Weiying Ding, Cupertino, CA (US);

Brad Vest, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, unknown;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H06F 11/00 (2006.01); G11B 5/09 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention includes techniques for programming and verifying data in a programmable circuit. Programmable circuits such as PLDs may include a plurality of rows and columns of memory cells. Data is programmed into memory elements associated with the rows and columns. Subsequently, the programmed data may be extracted for verification. A first word line may be selected by first word line address bits in row shift registers. Data programmed into the first word line is loaded into column shift registers for verification during one or more verify steps. During a program step, data is programmed into memory elements in a second word line that is selected by the first word line address bits. The present invention also provides a technique for shifting program data bits into the column shift registers at the same time that verify data bits are shifted out of the column shift registers.


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