The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2006

Filed:

Oct. 09, 2001
Applicants:

Tony M. Brewer, Plano, TX (US);

Christopher P. Davies, Dallas, TX (US);

Thomas C. Mcdermott, Iii, Richardson, TX (US);

Allen F. Rozman, Richardson, TX (US);

Inventors:

Tony M. Brewer, Plano, TX (US);

Christopher P. Davies, Dallas, TX (US);

Thomas C. McDermott, III, Richardson, TX (US);

Allen F. Rozman, Richardson, TX (US);

Assignee:

Chiaro Networks Ltd., Richardson, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 3/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A repetitive burst-mode input signal that has a dark time portion, a preamble portion, and a payload portion is converted into a limited output signal in accordance with a decision threshold level, which is controlled by selectively coupling an averaged value of the burst-mode data amplitude to the decision threshold level. The timing sequence for selectively coupling the averaged signal value is controlled such that the average value of the burst-mode signal acquired during the preamble portion of the burst-mode signal is applied to the decision threshold level during substantially all of the payload portion. The control circuit may incorporate a phase-locked loop, which locks onto the repetitive dark time frequency and in response synthesizes a switchable track enable signal that controls the timing sequence of the decision threshold level. The phase-locked loop can employ all-digital, analog, and/or hybrid digital/analog circuitry.


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