The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Mar. 22, 2004
Johnson Tan, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Philip Pan, Fremont, CA (US);
Yan Chong, Mountain View, CA (US);
Joseph Huang, San Jose, CA (US);
Johnson Tan, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Philip Pan, Fremont, CA (US);
Yan Chong, Mountain View, CA (US);
Joseph Huang, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.