The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2006

Filed:

Dec. 30, 2002
Applicant:

Jong-tae Kwak, Kyoungki-do, KR;

Inventor:

Jong-Tae Kwak, Kyoungki-do, KR;

Assignee:

Hynix Semiconductor Inc., Kyungki-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The apparatus includes: a delay line unit for receiving external clock signal and generating first and second delayed internal clock signals by delaying the external clock signal; a duty error controller for receiving the first and second delayed clock signals and outputting a first duty controlled clock signal and second duty controlled clock signal by shifting edges of the first and second delayed internal clock signals; and a delay model unit for compensating a delay of the duty controlled clock signal by estimating a delay amount of system. The present invention can correct the duty error by using the phase mixer and generate an internal clock signal having 50% of duty cycle.


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