Phase synchronization circuit

Abstract

In a phase sync circuit () which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit () of a dual loop configuration including both a phase comparison circuit () and a frequency comparison circuit (), a phase sync circuit () capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit () to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop Fto bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.