The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Sep. 26, 2002
Jarie Bolander, Redwood City, CA (US);
Steven P. Larky, Del Mar, CA (US);
Jarie Bolander, Redwood City, CA (US);
Steven P. Larky, Del Mar, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A method, system, and computer program product for designing an integrated circuit. In one example, a standard library is provided having a plurality of standard circuit cells, and a substitute library is provided having a plurality of substitute circuit cells wherein one or more substitute circuit cells correspond to one or more standard circuit cells and the one or more substitute circuit cells have at least one differing electrical characteristic—such as power consumption, quiescent current consumption, speed/response time, leakage current, etc.—than the corresponding one or more standard circuit cells. An initial circuit design is created using the plurality of standard circuit cells of the standard library; and one or more non-critical timing paths are identified in the initial circuit design, the non-critical timing paths including one or more standard circuit cells. The one or more standard circuit cells in at least one of the non-critical timing paths of the initial circuit design are replaced with one or more substitute circuit cells to form a modified integrated circuit design. The replacement operation may occur after standard circuit cells of the initial circuit design have been placed and routed. In this manner, the modified circuit design may include standard cells on the critical timing paths and substitute cells on the non-critical timing paths wherein the standard cells are faster and the substitute cells consume less power and/or less quiescent current, in one example.