The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2006

Filed:

Apr. 10, 2003
Applicants:

Krisztian Flautner, Cambridge, GB;

David T. Blaauw, Ann Arbor, MI (US);

Trevor N. Mudge, Ann Arbor, MI (US);

Nam S. Kim, Ann Arbor, MI (US);

Steven M. Martin, Ann Arbor, MI (US);

Inventors:

Krisztian Flautner, Cambridge, GB;

David T. Blaauw, Ann Arbor, MI (US);

Trevor N. Mudge, Ann Arbor, MI (US);

Nam S. Kim, Ann Arbor, MI (US);

Steven M. Martin, Ann Arbor, MI (US);

Assignees:

ARM Limited, Cambridge, GB;

University of Michigan, Ann Arbor, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.


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