The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Oct. 28, 2003
Douglas C. Buhler, Loveland, CO (US);
John Howard Cook, Iii, Fort Collins, CO (US);
Douglas C. Buhler, Loveland, CO (US);
John Howard Cook, III, Fort Collins, CO (US);
Agilent Technologies, Inc., Palo Alto, CA (US);
Abstract
A circuit and method is provided for determining the delay of an integrated circuit common associated with chip-to-chip variations in the manufacturing process, changes in operating voltage, and fluctuations in temperature. A clock signal is inverted, thus generating an inverted clock signal which is then delayed multiple times, resulting in several delayed versions of the inverted clock signal, with each version being delayed a different length of time. The logical state of each delayed version of the inverted clock signal is then stored. That stored logical state provides an indication as to the magnitude of the delay of the integrated circuit which may then be used to tune critical signals of the integrated circuit to avoid timing problems resulting from variations in IC propagation delay.