The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7051313 B1

PDF
Full Text
Expired
Date of Patent:
May. 23, 2006

Filed:

Aug. 13, 2003
Applicants:

Vaughn Betz, Toronto, CA;

Jonathan Rose, Toronto, CA;

Inventors:

Vaughn Betz, Toronto, CA;

Jonathan Rose, Toronto, CA;

Assignee:

Altera Toronto Co., Halifax, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An 'architecture generation engine' is operative with a CAD system to implement circuits into PLD (programmable logic device) architectures and to evaluate performances of different architectures. The architecture generation engine converts a high level, easily specified description of a PLD architecture into a highly detailed, complete PLD architecture database that can be used by a CAD toolset to map a circuit netlist into a PLD. The architecture generation engine also enables performance evaluation of a wide variety of PLD architectures for given benchmark circuits.


Find Patent Forward Citations

Betz, Vaughn. (2006). Automatic generation of programmable logic device architectures (U.S. Patent No. 7051313). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7051313

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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