The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Jun. 24, 2003
Anirban Rahut, San Jose, CA (US);
Sudip K. Nag, San Jose, CA (US);
Anirban Rahut, San Jose, CA (US);
Sudip K. Nag, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Within a computer automated tool, a method () of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying () a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining () an initial routing of the clock domain. The method also can include determining () a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode () allowing sharing of routing resources by different nets.